For memory transfer operations between different memories or parts of memory, a processor may use programmed input and output instructions to read, write, and set data. However, such instructions carried out by the processor may be slow due to latency of memory access. Access of memory might require physical interface with mechanical or electronic elements of the memory. The instruction, performed by the processor, will not end until the read or write is finished. The processor is thus waiting on the instruction to end which, as described above, may be slow to perform because of the memory latency. The processor, or the thread of the processor assigned to the task, may be unavailable to perform other tasks during this operation.
DMA may allow the processor to offload writing or reading blocks of data between memory locations. DMA may be implemented by a separate controller or circuit. The DMA controller may have an interface through which the processor or peripherals of a system may call the DMA controller to read or write the blocks of data. The processor or peripherals may perform other tasks while the DMA controller is operating to read or write blocks of data. When the DMA controller is finished, the DMA controller may issue an interrupt or other signal to the processor or peripheral.